Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.) Filing date Publication date Priority claimed from JP62-25725 external-priority Application filed by Toshiba Corp filed Critical Toshiba Corp Assigned to KABUSHIKI KAISHA TOSHIBA, A CORP.
Original Assignee Toshiba Corp Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.) Expired - Lifetime Application number US07/151,231 Inventor Masaji Ueno Current Assignee (The listed assignees may be inaccurate. Google Patents Bi-MOS logic circuit having a totem pole type output buffer sectionĭownload PDF Info Publication number US4845386A US4845386A US07/151,231 US15123188A US4845386A US 4845386 A US4845386 A US 4845386A US 15123188 A US15123188 A US 15123188A US 4845386 A US4845386 A US 4845386A Authority US United States Prior art keywords npn bipolar transistor mos bipolar transistor fet Prior art date Legal status (The legal status is an assumption and is not a legal conclusion.
Google Patents US4845386A - Bi-MOS logic circuit having a totem pole type output buffer section US4845386A - Bi-MOS logic circuit having a totem pole type output buffer section
